(1) Field of the Invention
The present invention relates to a MOS-type solid-state imaging device used for a digital camera or the like.
(2) Description of the Related Art
Various kinds of MOS-type solid-state imaging devices have been suggested in the past (see reference to Japanese Laid-Open Publication No. 2003-046864).
FIG. 1 is a diagram showing the structural example of the conventional solid-state imaging device that is made up of MOS transistors. The solid-state imaging device 22 is formed on a semiconductor substrate and is comprised of the following: a photodiode unit (to be referred to as “PD unit” hereinafter) 1 for performing photoelectric conversion on an incident light; a read transistor 2 for reading out a signal charge obtained by the PD unit 1; a floating diffusion unit (to be referred to as “FD unit” hereinafter) 7 for accumulating the signal charge read out by the read transistor 2; a detecting transistor 4 for detecting the signal charge accumulated by the FD unit 7; a reset transistor 3 for resetting the signal charge accumulated by the FD unit 7; and an imaging area 8 (an area indicated by a dashed line in FIG. 1) where amplifier-type unit pixels, each having a vertical signal line 5 and a VDD power 6, are bi-dimensionally arranged. Here, the area indicated by a two-dotted chain line in FIG. 1 is “a pixel unit” (also referred to as “unit pixel”) 14 composing a circuit having one pixel as a unit.
The solid-state imaging device 22 is further comprised of: a horizontal shift register 9 for selecting a column of pixels by use of the vertical signal line 5; a vertical shift register 10 for selecting a row of pixels using the vertical signal line 5; a timing generation circuit 11 for providing a pulse necessary for a drive; and an output amplifier 12.
FIG. 2 is a pattern diagram which includes the cross section of the pixel unit 14 shown in FIG. 1. In FIG. 2, the PD unit 1, the VDD power 6 and the FD unit 7 are made of n-type semiconductors and are formed on a well layer 13 made of p-type semiconductor. The gate of the read transistor 2 and that of the reset transistor 3 are poly-silicon electrodes. It should be noted that the cross section of the detecting transistor 4 is not shown in FIG. 2, but the source and drain of the detecting transistor 4 are made of n-type semiconductors and the gate is a poly-silicon electrode. The VDD power 6 is connected to the drain of the detecting transistor 4 and the drain of the reset transistor 3.
FIG. 3 is a circuit diagram illustrating each of the elements shown in FIG. 2. The signal charge on which photoelectric conversion is performed by the PD unit 1 is accumulated by the PN junction capacitance 1a in the PD unit 1, and then, read out by the PN junction capacitance 7a in the FD unit 7 allowed by the read transistor 2. The electric potential of the FD unit 7, being mainly made up of PN junction capacitances, is determined according to the amount of the charges that are read out and the gate voltage of the detecting transistor 4 changes accordingly. As a result, a signal is retrieved as a change in the electric potential of the vertical signal line 5.
FIG. 4 is a diagram showing the drive timing of the conventional pixel unit 14. FIG. 4 shows how a voltage pulse of the VDD power 6 (to be referred to as “VDD pulse” hereinafter), a reset pulse of the N th row reset transistor 3 (to be referred to as “N th row reset pulse”), and a read pulse of the N th row read transistor 2 (to be referred to as “N th row read pulse”), and a reset pulse of (N+1) th reset transistor (to be referred to as “((N+1) th row reset pulse”) and a read pulse of (N+1) th row read transistor (to be referred to as “(N+1) th row read pulse”) respectively changes with time at the time of operating N th and (N+1) th rows.
FIGS. 5A-5G show the electric potential at the time T1 through T7 at each of the units in the pixel unit 14, corresponding to FIG. 4. It should be noted that the vertical line in FIG. 5A-5G show an upper level as “Low level” and a lower level as “High level”. Firstly, at the time T1 shown in FIG. 5A, the PD unit 1 holds a signal charge and both the gate of the read transistor 2 and the gate of the reset transistor 3 are at Low level while the VDD power 6 is at High level. At the time T2 shown in FIG. 5B, the FD unit 7 is set to High level of the voltage in the VDD power 6 since the gate of the reset transistor 3 rises to High level. At the time T3 shown in FIG. 5C, the charge held by the PD unit 1 is read out by the FD unit 7 since the read pulse falls to Low level. Here, a signal is retrieved as a change in the electric potential of the vertical signal line 5 resulted from the change in the gate voltage of the detecting transistor 4 due to the change in the electric potential of the FD unit 7. After the VDD power 6 falls to Low level at the time T4 shown in FIG. 5D, the FD unit 7 is set to Low level by the fact that the gate of the reset transistor 3 rises again to High level at the time T5 shown in FIG. 5E. At the time T6 shown in FIG. 5F, the gate of the reset transistor 3 is at Low level. At the time T7 shown in FIG. 5G, the VDD power 6 rises again to High level in order to detect a signal of the (N+1) th row. Similarly, at the time T8 through T14, the same operation as performed at the time T1 through T7 on the pixels in the N th row is repeated for the pixels in the (N+1) th row.
However, the existing technique might cause the error which will be explained below.
At the time T7 shown in FIG. 5G as described above, the voltage changes rapidly when the VDD power 6 rises again to High level. At the same time, the gate voltage of the reset transistor 3 fluctuates to have a positive potential due to the coupling capacitance 41 between the VDD power 6 and the gate of the reset transistor 3. Therefore, the gate of the reset transistor 3 opens and a part of the electrons held in the FD unit 7 flows over to the side of the VDD power 6 so that the electric potential of the FD unit 7 becomes positive. Due to the change in the electric potential of the FD unit 7, the gate voltage of the detecting transistor 4 becomes positive and the detecting transistor 4 that is normally off is switched on. As a result, an error that the charge detected in the selectable row is affected by the selection of the non-selectable row is generated. Thus, a proper charge signal can not be obtained, and an error, for example, of not detecting a bright light, might be caused.